1. Field of the Invention
This invention relates to a decoder circuit for use in semiconductor memory devices such as MOS static RAMs etc., and more particularly, to a decoder circuit which is capable of lowering power consumption of a decoder circuit in a non-selective condition.
2. Description of the Prior Art
In general, various techniques for reducing power consumption in semiconductor memory devices have been attempted, for example, with a known representative method, such as described in Integrated Scratch Pads Sire New Generation of Computers, Electronics, Apr. 4, 1966, pages 118-126, wherein power consumption of the peripheral circuits is reduced by disconnecting the control signal power supply lines from the peripheral circuits (including decoder circuit, write circuit, read circuit) of the non-selected memory cells. The aforementioned control signal is sometimes called the chip select signal and is used for the control which connects the power supply line to the peripheral circuit of the selected memory chip. However, only one bit or several bits of the memory cells are actually selected in the selected memory chip and the decoder circuit to be selected therewith also functions as a decoder for one or more bits. Other decoder circuits are all in a non-selected condition. The decoder circuit is generally a NOR gate in the MOS static RAM etc., resulting in large power consumption in the non-selected condition and this problem is not solved even using the power saving techniques of the above-mentioned chip select signal.
FIG. 1 outlines a known static RAM in which the static memory cell array 1 is comprised of the N.times.M memory cells arranged in the form of a matrix. The word decoder 2 selects any one of the word lines X.sub.0 to X.sub.(N-1), while the column decoder 3 selects any one of the bit lines Y.sub.0 to Y.sub.(M-1), thereby selecting the cell located at the intersection thereof, making it possible to read data being stored or to write data into the selected cell. Power consumption of such a static RAM becomes significant as memory capacity becomes large and in particular, the word decoder circuit which selects word lines is at a high level when the NOR gate for selecting addresses selects a word line or at a low level when it does not select an address. Consequently, there is always the difficulty of reducing power consumption of the semiconductor memory devices because the decoder circuit consumes more power in the low level than that in the high level and the number of word line selecting circuits in the non-selected condition surpass those in the selected condition.
A circuit shown in FIG. 2 is a typical example of a decoder circuit mentioned above. In this figure, A.sub.0 to A.sub.n are address signal inputs; transistors QA.sub.0 to QA.sub.n form a NOR gate, while transistor Q.sub.11 is the load of the NOR gate. The transistor Q.sub.13 is an inverter, while transistor Q.sub.12 is the load of the inverter. The transistors Q.sub.14 and Q.sub.15 form an output circuit. V.sub.cc is a power supply, while V.sub.ss is the return side line of the power supply. The transistors shown with the dot in the figure, i.e., the transistors Q.sub.11 and Q.sub.12, are depletion type MOS transistors. In the above circuit, since the address signals A.sub.0 to A.sub.n are all at a low level when the word line is selected, the output of the NOR gate (point a1) is at a high level and the output of inverter (point a2) becomes low level. This causes the transistor Q.sub.14 of the output circuit to turn ON while Q.sub.15 is OFF. The output WD 1 is switched to a high level and since no current flows into the transistor Q.sub.15 and the transistors QA.sub.0 to QA.sub.n, this circuit consumes less power. In case a word line is not selected, at least one of the address signals A.sub.0 to A.sub.n is at a high level and as a result, the point a1 is at a low level, while the point a2 is at a high level, making the transistor Q.sub.14 turn OFF, while Q.sub.15 is ON. In this case, since at least one of transistors QA.sub.0 to QA.sub.n is ON, a current flows, consuming power.
The decoder circuit of this conventional type has the disadvantage that it consumes a considerable amount of power because it consumes more power in the non-selected condition of a word line than that in a selected condition and the circuits in the non-selected condition surpass in number those in the selected condition.